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42.7.2 PCB Surface Finishes and Solderability Testing for Plated Through Holes The one area where dip and look type testing works better over a wetting balance is in the examination of solderability of plated through holes. While the majority of assembly is surface mount, there remain a large number of connectors that are through-holes as well as other devices capacitors etc that are still assembled with wave soldering or intrusive paste reflow. Verification of through holes solderability is equally important if line defects are to be prevented. A solder float is still the preferred method as this forces the solder to rise against gravity to wet the plated through-hole. A number of points need to be made: 1. There are no requirements saying that vias need to be filled with solder sometimes they do, sometimes they do not.The size of the via and of the solder mask clearance defining the

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FIGURE 42.12 The gradual reduction in wetting forces for an OSP deposit after 22 months in unprotected storage. This shows the growth of the copper oxide layer which is obviously less solderable than an oxide-free copper surface.

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via, are key factors that influence whether they wet or not. The surface finish, however; must be plated inside the vias if required by the specification or purchase order. With the exception of tin-lead surface finish HASL there is no requirement to produce a positive meniscus for meeting class 3 acceptability. The solder should wet the hole completely, but it does not have to show positive meniscus. The requirement to have flux wet the hole and drain, while may be seen as stating the obvious, cannot be overstated. The flux needs to be adjusted to the specified specific gravity to allow for wetting to occur. If the holes are small or the aspect ratio is high, additional agitation rather than a simple dunk will be required to ensure complete wetting of the hole wall with the flux. Additionally, the need to tap the sample to ensure complete drainage is also necessary. Failure to do both will result in either incomplete hole fill and/or non-wets: both of which are failures but a function of the test rather than the surface finish. Adhere strictly to the 2 2 coupon-size specification and if the sample has many power or ground planes or a heavy overall copper-rich PCB, use pre-heat! Hole fill with Pb-free alloys are typically more difficult and may require an increase in test time to allow for the final outcome of the test hopefully complete hole fill. Experiment

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Supplier Survey Once these facts are known, a survey of potential tool suppliers must be conducted. Basic elements include: 1. Determining how closely each tool candidate comes to meeting the need and its cost to acquire, set up, and maintain 2. Assessing the long-term viability of the supplier to ensure that the tool does not become an orphan should the supplier fail 3. Making a check with other users of the candidate tools to ensure that they perform as advertised

14.4.3 Benchmarking Representative benchmark designs need to be made on each candidate system to assess how well they are done. Depending on the size of the potential sale and the size of the benchmark design, a vendor may do the benchmark free of charge. If not, one should be prepared to pay for this valuable step in the evaluation process. Only after completing all of these evaluation steps is it possible to make an informed selection. Doing less, such as relying on an outsider to recommend tools or taking a vendor s word for it, carries the risk of owning a tool that delays development or, worse, having to repeat the selection process in the middle of a project.

14.4.4 Multiple Tools Knowing the wide variety of designs that may be encountered and the fact that virtually all CAD and CAE tools have been designed to be very good at some subset of design types, it is unrealistic to expect that a single set of tools from a single vendor will be able to deal with all problems equally well. A company with a wide range of design types, such as a company engaged in the design of computers and instrumentation, should expect to own more than one set of tools, each set optimized to its set of tasks. Trying to force one set of tools onto all types of problems is certain to result in overtooling simple designs and undertooling complex ones.

rjmp RESET rjmp RESET rjmp RESET RESET: ldi r16, 0b11111111 out DDRB, r16 loopit: ldi r16, 0 out PORTB, r16

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